Method of providing a structure using self-aligned features

ABSTRACT

In a copper plating process, a seed layer is uniformly deposited over a surface, including lining a high aspect ratio trench defined by that surface. A mask layer is provided using a process that fails to deposit in the trench. In one exemplary embodiment, the failure is due to the decrease in the isotropic flux of neutrals toward the bottom of the trench. Copper is subsequently electroplated. Because the seed layer is exposed only within the trench, copper deposits only therein. The self-aligned mask prevents plating outside of the trench. A chemical-mechanical planarization step removes the mask and the seed layer extending beyond the trench, leaving a copper structure within the trench. The structure may serve as a conductive line, an interconnect, or a capacitor plate.

RELATED APPLICATION

This application is a divisional of U.S. application Ser. No.10/860,939, filed Jun. 3, 2004; which is a continuation of U.S.application Ser. No. 10/295,536, filed Nov. 15, 2002 and issued as U.S.Pat. No. 6,759,330; which is a divisional of U.S. application Ser. No.09/644,254, filed Aug. 22, 2000 and issued as U.S. Pat. No. 6,511,912.

TECHNICAL FIELD

The present invention relates generally to a method of fabricatingsemiconductor devices. More particularly, the present invention relatesto a method of self-aligned plating of copper.

BACKGROUND OF THE INVENTION

In fabricating a semiconductor device, it may be desirable to includecopper as part of the device due to copper's low resistivity and abilityto carry high current densities. Unfortunately, the use of copper issomewhat problematic. For instance, attempting to deposit a relativelylarge amount of copper directly onto a dielectric material results inpoor adhesion. This can be particularly troublesome if the underlyingsurface has a variable topography, such as an insulating surfacedefining a trench. Assuming that it is desirable to fill the trench withcopper, one known method of accomplishing this task is to first line thetrench with a seed layer, which provides nucleation sites for thesubsequent formation of copper. Known materials for such a seed layerinclude copper itself or aluminum. One known method of depositing theseed layer is physical vapor deposition (PVD). Such a process, however,not only lines the trench but also deposits the seed layer on surfacesoutside of the trench.

Once the seed layer has been deposited, copper is then provided usingone of several methods, such as electroplating. In that method, thein-process semiconductor device, which may still be part of an undicedsemiconductor wafer, is exposed to a solution containing ions of themetal to be deposited. The wafer serves as the cathode and is connectedat its edges to a negative terminal of a power supply. A suitable anodeis also exposed to the solution and is connected to a positive terminalof the power supply. The power supply generates an electrical currentwhich flows between the anode and the cathode through the solution. Theelectrical current causes an electrochemical reaction at the surface ofthe wafer, resulting in the metal ions in the solution being depositedthereon. Electroless deposition is also another option, whereindeposition occurs in an aqueous medium through an exchange reactionbetween metal complexes in solution and the particular metal to becoated; and an externally applied electric current is not required.

Regardless of the precise deposition process chosen, it is noteworthythat copper will deposit wherever the seed layer is exposed, includingoutside of the trenches, where copper is not necessarily desired. Thus,the excess copper must be removed using a process such aschemical-mechanical planarization (CMP). Doing so, however, may requiremultiple CMP steps depending upon the amount of excess copper to beremoved and the presence of other layers, such as a barrier layer. Thisruns counter to the general desire in the art, which favors a minimumnumber of process steps, minimal process time, and the minimal use ofmaterials such as CMP slurry and copper. In addition, attempts to removethe copper outside of the trench using CMP risks the phenomenon known as“dishing” concerning the copper remaining in the trench. Thisundesirable effect is further discussed in U.S. Pat. No. 6,080,656 byShih et al. (hereinafter Shih).

Shih also proposes a solution to the dishing problem. After depositing acopper seed layer over a dielectric layer defining a trench, Shihproposes depositing a continuous insulating layer over the dielectriclayer. Shih then patterns the insulating layer using photolithography inorder to remove the portions of insulating material over the trench.Shih suggests using the same photo mask used to define the trench in thedielectric. Ideally, only the portion of the seed layer within thetrenches remains exposed as a result of this process. Copper issubsequently electroplated and, because the portion of the seed layerexternal to the trench is covered by the insulating layer, plating doesnot occur in that location. Rather, plating is limited to the trenches.The purported result is a relatively easier CMP process that need onlyremove a small amount of copper, the insulating layer, and the seedlayer. However, Shih's process requires that the photolithography stepused to pattern the insulating layer be in perfect alignment with thephotolithography step used to define the trenches in the dielectric.Otherwise, copper will form outside of the trench and copper formationinside the trench will be hindered. Moreover, assuming that suchalignment is achieved, Shih's process still requires additionallithography and etching steps. As discussed above, there is anever-present desire in the art to minimize the number of process stepsneeded to fabricate a semiconductor device.

Other fabrication problems occur in another, seemingly unrelated, areaof semiconductor device fabrication; namely, plasma-assisted depositionprocesses such as plasma-enhanced chemical vapor deposition (PECVD).Ideally, generating a plasma as part of the deposition process resultsin neutral particles that enhance deposition upon the surface of aworkpiece. However, even with the enhancement that a plasma processprovides, other factors may interfere with deposition. One such factoris the aspect ratio defined by a portion of the surface. The aspectratio is defined as the depth of a feature divided by the width of afeature. If the surface defines a feature with a high aspect ratio, suchas a deep trench with a narrow width, it is theorized that the isotropicflux of neutrals will decrease within the trench, thereby preventingdeposition therein. In some circumstances, deposition does not occur atall within the trench.

This non-conformal deposition is an undesirable result in many instancesof fabrication. For example, there are efforts in the art to use aplasma process in order to deposit polymer on the sidewalls of a trench.Doing so allows a decrease in a dimension of a feature. As a result,there are efforts by those skilled in the art to change theplasma-enhanced deposition process to allow a more uniform deposition.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-4 are cross-sectional views of an in-process semiconductordevice depicting an exemplary process within the scope of the currentinvention.

FIG. 5 is a cross-sectional view of an in-process semiconductor devicedepicting an application of an exemplary process within the scope of thecurrent invention.

FIGS. 6-8 are cross-sectional views of an in-process semiconductordevice depicting another exemplary process within the scope of thecurrent invention.

FIGS. 9-12 are cross-sectional views of an in-process semiconductordevice depicting yet another exemplary process within the scope of thecurrent invention.

FIGS. 13-15 are cross-sectional views of an in-process semiconductordevice depicting still another exemplary process within the scope of thecurrent invention.

FIGS. 16-19 are cross-sectional views of an in-process semiconductordevice depicting one more exemplary process within the scope of thecurrent invention.

FIG. 20 is a cross-sectional view of an in-process semiconductor devicedepicting another application of an exemplary process within the scopeof the current invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates an in-process semiconductor device as known in theart, wherein an oxide 10 defines a trench 12, and a continuous seedlayer 14 about 1000 angstroms thick has been deposited thereover. It ispreferred that the trench define an aspect ratio of greater than 0.5.The oxide 10 is over a semiconductor substrate 13. In the currentapplication, the term “substrate” or “semiconductor substrate” will beunderstood to mean any construction comprising semiconductor material,including but not limited to bulk semiconductive materials such as asemiconductor wafer (either alone or in assemblies comprising othermaterials thereon), and semiconductive material layers (either alone orin assemblies comprising other materials). Further, the term “substrate”also refers to any supporting structure including, but not limited to,the semiconductive substrates described above. Moreover, it isunderstood that a semiconductor device may comprise conductive andinsulative materials as well as a semiconductive material.

For purposes of explanation, it is assumed that it is desired to fillthe trench with copper. Accordingly, it is further assumed that the seedlayer comprises copper and was deposited by a PVD process, as is knownin the art. As discussed above, prior art teaches either subsequently(1) plating over the entire surface, including outside of the trench; or(2) layering insulation over the entire surface and subsequentlypatterning that layer in an attempt to expose only the trench to theplating process.

At least one exemplary embodiment of the current invention, however,avoids both plating outside of the trench and having to pattern amaterial over the seed layer. Instead, a material 16 is deposited overthe seed layer under parameters such that the material 16 avoids thetrench 12. The result of such a deposition is illustrated in FIG. 2. Thematerial 16 is one that is capable of surviving a subsequent processthat adds to the inside of the trench 12. Again, for purposes ofexplaining the current invention, it is assumed that the subsequentprocess is a plating process. Accordingly, material 16 could be adielectric. More specific examples of material 16 include one comprisinga hydrocarbon, a fluorocarbon, or a fluorohydrocarbon. Assuming thatmaterial 16 is a dielectric such as a fluorocarbon polymer film, anexemplary deposition process that avoids the trench 12 can occur in anIPS etcher manufactured by Applied Materials, Inc. Exemplary parametersinclude introducing CH₂F₂ gas at a flow rate ranging from 20-60 sccm,preferably 40 sccm; a pressure ranging from 1 to 40 mTorr, preferably 25mTorr; a source power ranging from 600 W to 1500 W, preferably 1000 W; abias power of about 0 W; a roof temperature of about 140° C.; and anouter ring temperature of about 200° C.

Once the in-process device illustrated in FIG. 2 is achieved, theplating process mentioned above is carried out. In an exemplary platingprocess, electrical contact is made with the seed layer 14 at the edgeof the wafer, wherein the wafer has a face on which the semiconductordevice is being formed. The wafer is placed face-down at the opening ofa tank filled with a liquid comprising copper sulfate, sulfuric acid,hydrochloric acid, and organic additives. The wafer serves as a cathode,and an anode is found within the tank. The anode and cathode are 1 to 5cm apart, preferably 3 cm. The liquid in the tank flows from the bottomof the tank, around the anode, toward the tank opening where the waferis located, and spills out of the tank after contacting the wafer'sface. The flow rate of the liquid ranges from 2 to 7 gallons per minute(gpm), preferably 5.5 gpm. A current ranging from 2 to 8 amps isgenerated for 1 to 7 minutes. Preferably, a current of 4 to 5 amps isgenerated for 1 minute, and a current of 6 amps is subsequentlygenerated for 3 minutes. The waveform can be a pulse, direct current(DC), or a reverse pulse waveform; preferably a DC waveform is used. Thewafer is rotated at a rate of 20 to 70 rotations per minute (rpm),preferably 40 rpm. The result of this process is illustrated in FIG. 3,wherein copper 18 plates the trench 12 but does not plate outside of thetrench 12 because material 16 was deposited in such a manner so as toisolate a portion of the seed layer 14 external to the trench 12 fromthe plating fluid.

A removal step, such as CMP, may then be used to remove the material 16and the seed layer 14 external to the trench 12, resulting in thestructure appearing in FIG. 4. Exemplary CMP parameters include applyinga pressure of 2 to 5 pounds per square inch (psi) against the wafer,preferably 3 psi; a pad rotation rate ranging from 30 to 100 rpm,preferably 80 rpm; a wafer rotation rate ranging from 30 to 100 rpm,preferably 80 rpm; a slurry flow rate ranging from 50 to 200 millilitersper minute, preferably 100 milliliters per minute; and a temperatureranging from 70 to 130° F., preferably 77° F. The slurry itselfcomprises an abrasive such as SiO₂, Al₂O₃, TiO₂, or CeO₂; Al₂O₃ ispreferable. The slurry may also contain an oxidizer such as H₂O₂, KIO₃,FeNO₃, ammonium persulfate, or ammonium molybdate; H₂O₂ is preferable.The pH of the slurry can range from 2 to 10 and is preferably 7. The CMPcontinues until the material 16 and the seed layer 14 external to thetrench 12 are removed. An exemplary time required for such a result is60 seconds. One skilled in the art can now appreciate that removingmaterial 16 and seed layer 14 is preferable to removing a relativelythick layer of plated copper in terms of process time, amount of slurryused, and amount of copper wasted.

The basic process disclosed above can have applications at severalstages during semiconductor device fabrication. Such stages include wordline, bit line, plug, and interconnect formation. Exemplary embodimentsof the current invention include within their scope those comprising onesuch stage, combinations of such stages, and all stages.

For instance, the entrenched copper 18 of FIG. 4 could serve as a wordline/transistor gate 30, as seen in FIG. 5, by removing the oxide 10 andadding an oxide or nitride cap 20, adding dielectric spacers 22, anddefining active areas 24 using a doping process. Subsequent fabricationsteps involve providing a second oxide 26 and etching openings 28 in thesecond oxide 26 down to the active areas 24. At this stage, it isdesired to fill the openings 28 with a material that will allowelectrical communication between the active areas 24 and conductivestructures to be provided over the second oxide 26.

The conductive structures that fill the openings and allow suchcommunication are often referred to as “plugs” and can be formed in amanner similar to that used to form the transistor gate 30. As seen inFIG. 6, a second seed layer 32 is provided over the second oxide 26, anda second dielectric 34 is deposited in a manner so as to avoid portionsof the seed layer 32 lining the openings 28. As seen in FIG. 7, aplating process or some other deposition method is used to deposit anelectrically conductive material 36 only on the exposed portions of seedlayer 32. A subsequent CMP step can be used to remove the seconddielectric 34 and portions of the second seed layer 32 external to theopenings 28, resulting in the in-process device including plugs 38 seenin FIG. 8.

As an alternative or addition to forming the gate 30 and plugs 38 usingthe steps of non-selectively depositing a seed layer and selectivelydepositing a dielectric layer, such steps can be used to form one orboth electrodes of a capacitor. FIG. 9 illustrates that a third oxide 40is deposited over the second oxide 26 and a container 42 is defined fromthe third oxide 40. In this example, defining the container 42 comprisesetching the third oxide 40 as guided by a patterned mask 43, such as anitride mask. The mask 43 need not be removed immediately after definingcontainer 42, as it can be removed later in the same process that willremove other layers, as detailed below. FIG. 10 shows that a third seedlayer 44 is deposited so that it conforms to the underlying surfaces,including lining the container 42. For purposes of explanation, it isassumed that the third seed layer 44 comprises platinum and is depositedby a PVD process. A third dielectric 46 is deposited so that it formsonly in regions external to the container 42. Subsequently, a layer ofplatinum, serving as a first electrode 48 and depicted in FIG. 11, isplated onto the exposed third seed layer 44 using methods known in theart. A subsequent CMP step removes the third dielectric 46, portions ofthe third seed layer 44 external to the container 42, and the mask 43,yielding the in-process device seen in FIG. 12.

Next, as indicated by FIG. 13, a capacitor dielectric 50 is formed overat least the first electrode 48. A fourth seed layer 52, againcomprising platinum, is deposited by way of PVD over the capacitordielectric 50. A fourth dielectric 54 is selectively deposited ontoportions of the fourth seed layer 52 that are outside of the container42. A subsequent plating process selectively deposits platinum, whichserves as a second electrode 56 (FIG. 14). It should be noted that, inmany semiconductor circuits, this second electrode serves as a cellplate node that is in electrical communication with a plurality ofcapacitors. As a result, when performing a CMP step, as has been done inexamples discussed above, it may be desirable in this example to stopthe CMP step once the fourth dielectric 54 has been removed and retainthe fourth seed layer 52 (FIG. 15). This is easily accomplished if theseed layer comprises platinum—a noble metal—which is resistant to CMP.

Another stage in which the disclosed process may be used is illustratedbeginning with FIG. 16. This stage concerns the formation of a bit linecontact. The fourth seed layer 52 and capacitor dielectric 50 areremoved from an area above one of the plugs 38, and a fourth oxide 58 isplaced in that area as well as areas above the fourth seed layer 52 andcapacitor dielectric 50. A contact opening 60 is etched through thefourth oxide 58 and the third oxide 40 down to one of the plugs 38. FIG.17 demonstrates that a conformal fifth seed layer 62 that lines thecontact opening 60 is provided, as is a non-conformal fifth dielectric64. Accordingly, a subsequent plating process deposits metal 66 onlywithin the contact opening 60 (FIG. 18), thereby forming a bit linecontact 68. It should be noted that the plug 36 under bit line contact68 is not necessary for purposes of this exemplary embodiment: theformation of that plug 36 could be skipped and the bit line contact 68could be formed so that it extends all the way to the underlying activearea 24.

Once the fifth dielectric 64 and fifth seed layer 62 have been removedusing a process such as CMP (FIG. 19), the bit line itself 70 (FIG. 20)may be provided in a similar manner.

As mentioned above, exemplary embodiments of the current inventioninclude any one or any combination of the stages described above.Further, one of ordinary skill in the art will appreciate that, althoughexemplary embodiments of this invention have been described above forpurposes of illustration, various modifications may be made withoutdeparting from the spirit and scope of the invention. For example,materials other than platinum or copper can be provided using thetechniques described above. Such other metals include silver, gold,cobalt, nickel, non-metals, non-conductive materials, and in general anymaterial that benefits from a seed layer, as well as combinations ofmaterials.

Further, exemplary embodiments of the current invention are not limitedto the plasma process addressed above. Other plasma processes, oftenreferred to as “high density” or “decoupled” plasma processes may beused in embodiments of the current invention. In fact, any depositionprocess that uses a plasma without applying substantial amounts ofcapacitively coupled power through the wafer could be used in suchembodiments. For instance, embodiments of the current invention may beapplied to a plasma process wherein the capacitively coupled powerthrough the wafer is 20% or less than the total power delivered to thechamber.

In addition, plasma process are not the only deposition processes thatcould be used to provide a masking material outside of the trench. Anyprocess that provides the appropriate non-conformal material could beused. For instance, reacting silane with vaporized hydrogen peroxideresults in a gas which condenses as a liquid on a substrate cooled toabout 0° C. The condensation is non-conformal, as portions of the liquidon horizontal surfaces are thicker than portions of the liquid onvertical surfaces. A subsequent heat treatment dries the liquid to formSiO₂. Given a support surface defining a trench and an ambienttemperature during deposition approaching 100° C., it is believed thatthe non-conformal oxide will deposit only at the top of a trench to theexclusion of the sides and bottom of the trench.

Moreover, in addition to the layers addressed above, other layers may beincluded during the fabrication process to serve as diffusion barriersor to promote electrical communication. In fact, the presence of abarrier layer highlights the advantages of at least some embodiments ofthe current invention. Specifically, it is known in the art to deposit aconformal layer of tantalum before depositing a seed layer and platingcopper. The tantalum acts as a barrier to copper diffusion. Assumingthat copper is plated both within and without the trenches, one skilledin the art must then remove both copper and tantalum from regionsoutside of the trenches. Further assuming that the unwanted copper andtantalum will be removed by way of CMP, one skilled in the art has achoice of three main types of slurry. A first type is effective againstcopper but generally ineffective against tantalum; for example, EP-C5001from Cabot Corporation will remove Cu at 6000A/minute and will notremove Ta. A second type is effective against tantalum but generallyineffective against copper; EP-C4200A from Cabot corporation, forinstance, will remove Ta at 500A/min and will not remove Cu. A thirdtype works on both copper and tantalum, but the copper removal rate isstill relatively low. In general, a low removal rate for copper isconsidered to be about 1000A/min or less. As a specific example of thisthird type of slurry, Cu-10k-2 from Planar Solutions will remove both Cu(at 650A/min) and Ta (at 800A/min). The exact chemistry of theseslurries are trade secrets of the vendors selling them, but it isbelieved that the slurries are based on hydrogen peroxide and includedifferent additives.

Given the three types of slurries discussed above, a two-stage CMPprocess is often chosen, wherein the first type of slurry is initiallyused to remove the copper and stop on the tantalum. The slurry is thenswitched to the second type to remove the tantalum layer. The third typeof slurry would eventually remove both copper and tantalum without theneed to switch chemistries. However, one of ordinary skill in the artwould be discouraged from using this type of slurry. Given the amount ofcopper to be removed from the prior art in-process structure, the amountof time needed for this slurry to complete the CMP process would beunacceptable. Thus, up to now, one of such skill in the art has beenfaced with either (1) the problems associated with providing andswitching between multiple slurry chemistries or (2) the problemsassociated with one slowly acting slurry.

Exemplary embodiments of the current invention avoid both problems. Suchembodiments allow the use of the third type of chemistry. Because thereis a relatively low amount of copper to CMP—the seed layer and perhapssome plated copper extending up from the trench—the relatively lowcopper removal rate is inconsequential. Further, it is believed that theslurry will be effective in removing the self-aligned dielectric mask aswell. As a result, the two-step CMP process in the prior art issimplified to a one-step CMP process in exemplary embodiments of thecurrent invention.

Exemplary embodiments of the current invention, however, embrace theproblem of decreasing isotropic flux in a high aspect ratio feature byusing that phenomena to solve the copper plating problem. First, anin-process semiconductor device is provided. The device comprises amaterial defining a trench and a seed layer over the material. In oneexemplary embodiment of the current invention, a plasma process is usedto deposit a non-conformal mask onto the seed layer. The mask isnon-conformal in that it does not deposit inside the trench. Hence, theseed layer therein is exposed. The mask does cover portions of the seedlayer outside of the trench. As a result, a subsequent plating processdeposits a conductive material only inside of the trench. A CMP stepremoves the mask and seed layer external to the trench.

Alternative exemplary embodiments of the current invention involve theuse of phenomena other than decreasing isotropic flux in a high aspectratio feature to provide an appropriate non-conformal mask layer. Stillother embodiments concern the provision of materials other than copper.

In addition, exemplary embodiments of the current invention address theapplication of this process in at least one of several stages ofsemiconductor device fabrication, including forming a conductive linepredominantly at one elevation of a semiconductor device, providingelectrical communication between different elevations of a semiconductordevice, and forming at least one capacitor electrode.

Accordingly, the invention is not limited except as stated in theclaims.

1. A method of depositing a conductive material into a trench defined bya surface of a semiconductor device, said method comprising: coveringsaid surface of said semiconductor device with a seed layer, wherein aportion of said seed layer lines said trench; depositing a mask oversaid seed layer in a manner that exposes said portion of said seedlayer; and plating said conductive material onto said portion of saidseed layer.
 2. The method in claim 1, wherein said step of plating saidconductive material comprises plating a selection of copper, platinum,silver, gold, cobalt, and nickel.
 3. The method in claim 2, wherein saiddepositing step comprises providing a plasma.
 4. The method in claim 3,wherein said step of depositing a mask comprises depositing adielectric.
 5. A method of selectively depositing a conductive materialover a surface of a semiconductor device, said method comprising:selectively depositing a mask over a seed layer on said surface of saidsemiconductor device; and plating a metal over said surface, whereinsaid plating step is guided by said mask.
 6. The method in claim 5,wherein said step of plating a metal comprises plating a metal over atleast one unmasked portion of said surface.
 7. The method in claim 6,wherein said depositing step comprises depositing a mask onto the seedlayer outside a trench, wherein said seed layer is configured toencourage plating of said metal.
 8. The method in claim 7, wherein saidstep of depositing a mask onto the seed layer comprises depositing saidmask onto the seed layer comprising said metal.
 9. A method ofprocessing a semiconductor substrate comprising a first portion and acomplementary second portion, said comprising: selectively depositing afirst material over said first portion of said semiconductor substrate;selectively depositing a second material over a second portion of saidsemiconductor substrate; wherein said step of selectively depositing afirst material comprises depositing said first material over said firstportion to the exclusion of said second portion; and wherein said stepof selectively depositing a second material comprises depositing saidsecond material over said second portion to the exclusion of said firstportion.
 10. The method in claim 9, wherein: said step of selectivelydepositing a first material comprises depositing said first materialonly over said first portion; and said step of selectively depositing asecond material comprises depositing said second material only over saidsecond portion.
 11. The method in claim 9, wherein: said step ofselectively depositing a first material comprises depositing said firstmaterial at a first elevation over said semiconductor substrate; andsaid step of selectively depositing a second material comprisesdepositing said second material at at least a second elevation undersaid first elevation.
 12. A method of processing a circuit devicecomprising a surface defining a trench, said method comprising:depositing a non-patterned layer over said surface of said circuitdevice, wherein said layer exposes said trench; and adding a materialwithin said trench, wherein said material avoids said layer.
 13. Themethod in claim 12, wherein said depositing step comprises: refrainingfrom affirmatively patterning said layer; and allowing at least onefactor that inhibits conformal deposition to affect said depositingstep.
 14. The method in claim 13, wherein said allowing step comprisesallowing an aspect ratio defined by said trench to inhibit conformaldeposition of said layer.
 15. A method of managing a plurality ofslurries comprising a first slurry configured to react with copper at afirst rate and not with tantalum, a second slurry configured to reactwith tantalum and not with copper, and a third slurry configured toreact with tantalum and with copper at a second rate slower than saidfirst rate, said method comprising: providing a semiconductor workpiececomprising: a material defining a trench, a tantalum layer inside andoutside of said trench, a seed layer inside and outside of said trench,wherein said seed layer comprises copper, a mask layer outside of saidtrench and avoiding said inside of said trench, and copper inside ofsaid trench and avoiding an area immediately outside of said trench;refraining from exposing said workpiece to said first slurry and saidsecond slurry; and chemically-mechanically planarizing said workpieceusing said third slurry.
 16. A method of providing tantalum and copperin a trench defined by a support surface, said method comprising:depositing tantalum inside said trench and immediately outside saidtrench, depositing a first amount of copper inside said trench andimmediately outside said trench; depositing a second amount of copperinside said trench to the exclusion of depositing immediately outside ofsaid trench; and removing copper and tantalum immediately outside ofsaid trench in a single CMP step.
 17. The method in claim 16, furthercomprising: depositing a mask immediately outside of said trench to theexclusion of depositing inside said trench, wherein said step ofdepositing a mask comprises depositing said mask after said step ofdepositing a first amount of copper and before said step of depositing asecond amount of copper; and removing said mask after said step ofdepositing a second amount of copper.
 18. The method of claim 17,wherein said step of depositing a first amount of copper comprisesdepositing a copper layer about 1000 angstroms thick.
 19. The method inclaim 17, wherein said removing step comprises removing copper outsideof said trench at a rate of about 1000 angstroms per minute.
 20. Themethod in claim 17, wherein said removing step comprises removing copperoutside of said trench at a rate of at most 1000 angstroms per minute.21. The method in claim 20, wherein said removing step comprisesremoving copper outside of said trench at a rate of about 650 angstromsper minute.